The present invention relates in general to semiconductor devices and more particularly to a packaged semiconductor device having a package substrate supporting a semiconductor chip.
In a typical packaged semiconductor device, a semiconductor chip is mounted on a package substrate made of ceramic or heat resistant resin. In order to achieve the electric connection to external circuits, minute leads are provided on the semiconductor chip so as to project from the periphery thereof and these minute leads are connected to connection pins provided on the package substrate.
Electric connection between the minute leads and the connection pins are made conventionally either using a so-called wire bonding process wherein each of the minute leads is connected to a corresponding connection pin by a thin wire or using a process called wireless bonding. In the wireless bonding process, the semiconductor chip is mounted face downward, for example, to the substrate which is provided with a conductor pattern. This conductor pattern is connected to lead frames of the package substrate.
Alternatively, the minute leads of the semiconductor chip may be replaced by minute projections or bumps of electrically conductive material provided on the chip in correspondence to the connection pads of the chip, and the semiconductor chip thus formed with the bumps is pressed against the substrate face downward under a suitably chosen temperature such that the bumps on the semiconductor chip develop a firm mechanical as well as electric connection with corresponding leads provided on the package substrate. These leads are of course connected to the lead frames at the periphery of the package substrate.
There is another known process of wireless bonding wherein the semiconductor chip formed with the bumps is not mounted directly on the package substrate but instead mounted first on a thin conductor foil which is patterned according to a predetermined conductor pattern corresponding to the bumps. This conductor pattern includes a terminal part acting as the leads for making a contact with the corresponding leads on the package substrate. The conductor foil is supported by a perforated plastic tape having an appearance somewhat similar to a movie film. In each of the regions corresponding to the frame of the movie film, the conductor pattern for one semiconductor chip is provided and this pattern is repeated a number of times along the tape.
This last process is known as the TAB (tape automated bonding) process and is particularly suitable for automatic assembling of the packaged semiconductor device. As will be understood from the foregoing description, the TAB process includes two distinct steps, i.e. the first step of thermocompression bonding for pressing the semiconductor chip against the tape such that the bumps on the semiconductor chip are bonded to corresponding leads on the tape, and the second step of gang bonding for connecting the leads in the terminal part of the tape to the corresponding patterns on the package substrate. The former step is called the inner lead bonding or ILB process and the latter step is called the outer lead bonding or OLB process. Upon completion of the OLB process, the desired connection of the semiconductor chip to the lead frames of the package substrate is achieved. It should be noted that the number of semiconductor chips mounted on the package substrate is not limited to one.
Meanwhile, the number of terminals and thus the number of lead frames to be formed on the package substrate is increasing with increasing integration density of the semiconductor device. Associated therewith, there occurs rather frequently a case in which the number of connections which are provided by the lead frames at the periphery of the package substrate is insufficient. In order to provide a sufficient number of connections, a so called pin grid array (PGA) structure is proposed, wherein a number of connection pins are provided in a row and column formation on the package substrate so as to project from the bottom of the package substrate. In the semiconductor device having the PGA structure, connection pins in the number of several tens to several hundreds can be easily provided on the package substrate.
In association with the use of the PGA structure providing an increased number of connection pins, a layered conductor structure is provided on the package substrate in order to achieve an effective connection between the leads on the semiconductor chip and the connection pins. In this layered conductor structure, more than one conductor layer of thin metal or the like is provided with respective conductor patterns, and the conductor patterns of the different levels are interconnected by a hole.
FIG. 1 shows, in perspective, a prior art packaged semiconductor device 10 having a package substrate 12 on which a semiconductor chip 11 is mounted, and FIG. 2 is an enlarged view of a part 100 marked by a circle in FIG. 1. Referring to FIG. 1 or FIG. 2, the substrate 12 may be a ceramic substrate made of alumina or aluminum nitride. On the substrate 12, a layered conductor structure comprising two or more layers of conductors separated from each other by intervening insulator layers is provided. In the uppermost conductor layer of the layered conductor structure, there is formed a part 17 referred to hereinafter as a lead pattern comprising a number of thin conductor strips 17a-17g, so that each strip of the lead pattern 17 coincides with a corresponding lead 15 provided on the chip 11 by the TAB process. In this uppermost conductor layer, there is defined a lead pattern region 16 of length L for making contact with the leads 15. It should be noted that the semiconductor chip 11 is connected to the leads 15 by a solder bump 5 at the time of the TAB process. On the other hand, the lower conductor layer of the layered conductor structure is patterned into a number of pattern portions as will be described, and there is established an electrical connection between each of the pattern portions and a corresponding connection pin 19 provided on the package substrate 12.
It should be noted that the connection pins 19 are arranged in a row and column formation so as to project from the bottom surface of the substrate 12 through penetrating holes 12a. In other words, the semiconductor device 10 of FIG. 1 has the PGA structure. The conductor layers of different levels are connected to each other by a contact hole provided on the insulator layer. In a typical package, the number of the connection pins 19 provided on a single package substrate 12 may be several ten to several hundred. In correspondence to the increased number of the pins 19, the number of the conductor strips forming the lead pattern 17 may become several hundred. Thus, the conductor strips forming the lead pattern 17 are disposed with extremely small separation which may be less than 0.1 mm. In correspondence to the number of the conductor strips, the layered conductor structure provided on the package substrate 12 may include more than two layers of conductors.
FIG. 3 shows an example of the conductor pattern of the uppermost level and a lower level underlying the uppermost level conductor pattern in a same drawing. The part illustrated in FIG. 3 corresponds to a part 200 marked by a circle in FIG. 1. In the drawing, there are shown a lower level conductor layer 14 provided directly on the package substrate 12, an insulator layer 13 of polyimide and the like provided on the layer 14, and the lead pattern 17 provided on the insulator layer 13 as the uppermost level conductor layer. The conductor layer 14 is patterned into a number of portions respectively connected to corresponding connection pins 19 via the penetrating holes 12a extending through the package substrate 12.
FIG. 4 shows a cross-sectional view of the structure of FIG. 3 taken along a line 3--3'. As will be seen in FIG. 3, the lead pattern 17 formed in the uppermost level conductor layer is connected to the lower level conductor layer 14 via a contact hole 18, and the lower level conductor layer 14 is connected to the connection pin 19 by a conductive member 12b filling the penetrating hole 12a.
When such a layered structure is employed for the conductor pattern on the surface of the package substrate 12, there appears a tendency that the top surface of the lead pattern 17 at the uppermost conductor layer will vary. Particularly, as a result of the patterning provided in the lower layer 14, there appears a lateral gap g between adjacent conductor patterns of the lower conductor 14. When such a gap g is formed, the top surface of the insulator layer 13 is depressed and as a result, the level of the lead pattern 17 is inevitably decreased in correspondence to the gap g. As the lead pattern 17 is the part for making the contact with the leads 15 provided on the semiconductor chip 11, such a change in the level of the conductor layer results in the failure, of proper electrical as well as mechanical connection between the semiconductor chip and the connection pins 19.
In order to eliminate the problem of failure of the electrical connection, there is proposed to use a filler material or filler pattern 14a of an insulating material so as to fill the gap g between adjacent conductor layers 14. This filler patter 14a is illustrated in FIG. 2 and FIG. 3. By using the filler pattern 14a, the depression formed as a result of the absence of the conductor layer in the gap g is expected to be compensated and the decrease in the level of the lead pattern 17 in correspondence to the region of the gap g would substantially be reduced.
However, the control of the position and thickness of the filler pattern 14a is difficult because of the fine patterning of the lead pattern 17, and associated therewith, there occurs rather often a case in which the top surface of the lead pattern 17 on the gap g is still offset from the level of other lead patterns 17 as shown in FIG. 3 by an offset +/-.delta.. When the offset .delta. is negative and the level of the lead pattern 17 on the gap g is still lower than the level of other lead patterns 17, the electrical contact still fails as in the case of a lead pattern 17b in FIG. 2. On the other hand, when the offset .delta. is positive and the lead pattern 17 on the gap g is projecting upwards relative to other lead patterns 17 as in the case of a conductor strip 17e in FIG. 2, the lead pattern 17 may either be deformed laterally as illustrated or flattened at the time of the thermocompression bonding. Further, the pressure needed for the thermocompression bonding may be prevented from being transferred to the adjacent conductor strips 17d and 17f when the conductor strip 17e is projected upwards. Thus, the projection of the lead pattern 17 also gives the improper electrical connection. As the connection of the lead pattern 17 to the leads 15 on the semiconductor chip 11 is made by the gang bonding process, an offset of the level of even about 2-3 .mu.m is adversary to the reliable contact.
As described heretofore, such a projection or depression is inevitable in the lead pattern 17 particularly when it is provided on the layered conductor structure including the gap g in the lower level conductor layer 14. To make the matter worse, the gap g extends in a direction generally parallel to the conductor strips 17a-17g forming the lead pattern 17. Thus, in the case of FIG. 2, the failure occurs for substantially the entire length of the conductor strip 17b or 17e.